Computer architecture for software developers - Revision history

Daniel-schurhoff-de23@rwth-aachen.de at 14:18, 3 September 2019

2019-09-03T14:18:37Z

2019-07-04T14:07:37Z

Putting it all together

2019-07-04T13:46:39Z

Putting it all together

2019-07-04T13:46:12Z

Putting it all together

2019-07-04T12:59:21Z

Putting it all together

2019-07-04T12:58:15Z

Node topology

2019-07-04T12:58:01Z

System architecture

2019-07-04T12:56:16Z

Node topology

2019-07-04T12:43:38Z

Data parallel execution units

2019-07-04T12:43:23Z

Simultaneous multithreading

@@ Line 92: / Line 92: @@
 [[File:Performance core.png|500px]]
-For a Skylake processor with two FP FMA execution units <math>n^\text{FP}_\text{super}=2</math> and <math>n_\text{FMA}=2</math> and <math>n_\text{SIMD}=8</math> for double precision FP operations and using a AVX512 frequency of 1.9 GHz this results in a performance of 60.8 GF/s for a single core.
+For a Skylake processor with two FP FMA execution units <math>n^\text{FP}_\text{super}=2</math> and <math>n_\text{FMA}=2</math> and <math>n_\text{SIMD}=8</math> for double precision FP operations and using a AVX512 frequency of 1.9 GHz this results in a performance of 60.8 GF/s for a single core. This is an impressive performance, but if one misses out on one of the factors the performance drop is large. The serial performance not using FMA and SIMD is 7.6 GF/s (already accounting for the higher core frequency without SIMD), a performance level that is not different from cores 10 years ago. For the chip or node level performance the core count is simply multiplied with the single core performance.
 Simplified illustration of the Intel Skylake core architecture:

@@ Line 92: / Line 92: @@
 [[File:Performance core.png|500px]]
-For a Skylake processor with two FP FMA execution units <math>n^\text{FP}_\text{super}=2</math and <math>n_\text{FMA}=2</math and <math>n_\text{SIMD}=8</math for double precision FP operations and using a AVX512 frequency of 1.9 GHz this results in a performance of 60.8 GF/s for a single core.
+For a Skylake processor with two FP FMA execution units <math>n^\text{FP}_\text{super}=2</math> and <math>n_\text{FMA}=2</math> and <math>n_\text{SIMD}=8</math> for double precision FP operations and using a AVX512 frequency of 1.9 GHz this results in a performance of 60.8 GF/s for a single core.
 Simplified illustration of the Intel Skylake core architecture:

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 === Putting it all together ===
 [[File:Performance core.png|500px]]
 Simplified illustration of the Intel Skylake core architecture:

← Older revision		Revision as of 12:59, 4 July 2019
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	=== Putting it all together ===		=== Putting it all together ===
		+
		+	[[File:Performance core.png\|500px]]

	Simplified illustration of the Intel Skylake core architecture:		Simplified illustration of the Intel Skylake core architecture:

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 === Node topology ===
-[[File:Node-architecture.png|700px]]
+[[File:Node-architecture.png|600px]]
 == System architecture ==

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 == System architecture ==
 == Links and further information ==
 * John Hennessy David Patterson: [https://www.elsevier.com/books/computer-architecture/hennessy/978-0-12-811905-1 Computer Architecture] - A Quantitative Approach. Still the standard text book on computer architecture

← Older revision		Revision as of 12:56, 4 July 2019
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	=== Node topology ===		=== Node topology ===
		+
		+	[[File:Node-architecture.png\|700px]]

	== System architecture ==		== System architecture ==

← Older revision		Revision as of 12:43, 4 July 2019
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	SIMD was besides multicore a main driver for processor performance from 2005 to 2018. SIMD is still an important factor in the product that determines the core performance, but it is unlikely it is a driver for performance in the future.		SIMD was besides multicore a main driver for processor performance from 2005 to 2018. SIMD is still an important factor in the product that determines the core performance, but it is unlikely it is a driver for performance in the future.
		+
		+	==== Consequences for software developers ====

	=== Putting it all together ===		=== Putting it all together ===

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 Comparison of standard vs. 2-way SMT core:
 [[File:SMT-comparison.png|800px]]
 === Data parallel execution units ===