Make - Revision history

Daniel-schurhoff-de23@rwth-aachen.de at 13:50, 3 September 2019

2019-09-03T13:50:33Z

Jan-eitzinger-77c0@uni-erlangen.de: /* Working example */

2019-06-04T04:56:00Z

Working example

Jan-eitzinger-77c0@uni-erlangen.de: /* Working example */

2019-05-28T07:28:56Z

Working example

Jan-eitzinger-77c0@uni-erlangen.de: /* Common Pitfalls */

2019-05-28T07:27:59Z

Common Pitfalls

Jan-eitzinger-77c0@uni-erlangen.de: /* Advanced usage */

2019-05-28T07:24:50Z

Advanced usage

Jan-eitzinger-77c0@uni-erlangen.de: /* Basic usage */

2019-05-28T07:23:24Z

Basic usage

Jan-eitzinger-77c0@uni-erlangen.de at 07:19, 28 May 2019

2019-05-28T07:19:22Z

Jan-eitzinger-77c0@uni-erlangen.de: /* Tips and Tricks */

2019-05-24T12:22:03Z

Tips and Tricks

Jan-eitzinger-77c0@uni-erlangen.de: /* Common Pitfalls */

2019-05-24T12:21:21Z

Common Pitfalls

Jan-eitzinger-77c0@uni-erlangen.de: /* Common Pitfalls */

2019-05-24T12:20:51Z

Common Pitfalls

← Older revision		Revision as of 13:50, 3 September 2019
Line 1:		Line 1:
		+	[[Category:HPC-Developer]][[Category:HPC-User]]
	Make is a build automation tool, that can build arbitrary targets (in most cases program executables or libraries) from a list of prerequisites (which can be files or other targets). Make is controlled by reading files called Makefiles, which specify how to derive a target. While make is a standard UNIX tool, today in most cases people refer to the [https://www.gnu.org/software/make/ GNU make] implementation, which has a lot of extensions.		Make is a build automation tool, that can build arbitrary targets (in most cases program executables or libraries) from a list of prerequisites (which can be files or other targets). Make is controlled by reading files called Makefiles, which specify how to derive a target. While make is a standard UNIX tool, today in most cases people refer to the [https://www.gnu.org/software/make/ GNU make] implementation, which has a lot of extensions.

@@ Line 158: / Line 158: @@
 You can download a ready to use generic makefile for C/C++ and Fortran as well as mixed language projects including an example [https://github.com/RRZE-HPC/Code-teaching/releases/download/v1.0-demos/make-demo-1.0.zip here].
-For a working real example project including a configuration file you can have a look at ''The Bandwidth Benchmark'' [https://github.com/RRZE-HPC/TheBandwidthBenchmark teaching code].
+For a working real example project including a build configuration file you can have a look at ''The Bandwidth Benchmark'' [https://github.com/RRZE-HPC/TheBandwidthBenchmark teaching code].
 == Links and more Information ==
 * [https://www.gnu.org/software/make/manual/make.html#Rule-Introduction GNU make info pages] Probably the most complete and exhaustive documentation on make. Includes many examples.
 * An in-depth discussion of automatic make dependency generation can be found [http://make.mad-scientist.net/papers/advanced-auto-dependency-generation/ here]

@@ Line 158: / Line 158: @@
 You can download a ready to use generic makefile for C/C++ and Fortran as well as mixed language projects including an example [https://github.com/RRZE-HPC/Code-teaching/releases/download/v1.0-demos/make-demo-1.0.zip here].
-For a working real example project including configuration file you can have a look at ''The Bandwidth Benchmark'' [https://github.com/RRZE-HPC/TheBandwidthBenchmark teaching code].
+For a working real example project including a configuration file you can have a look at ''The Bandwidth Benchmark'' [https://github.com/RRZE-HPC/TheBandwidthBenchmark teaching code].
 == Links and more Information ==
 * [https://www.gnu.org/software/make/manual/make.html#Rule-Introduction GNU make info pages] Probably the most complete and exhaustive documentation on make. Includes many examples.
 * An in-depth discussion of automatic make dependency generation can be found [http://make.mad-scientist.net/papers/advanced-auto-dependency-generation/ here]

@@ Line 152: / Line 152: @@
 == Common Pitfalls ==
-The most common error in make is the message ''No rule to make target xxx.''. One must understand that make tries for every prerequisite to either find a file to match a rule that resolves it. Typical sources of reasons are typos in generated filenames or missing rules that resolve the prerequisite.
+The most common error in make is the message ''No rule to make target xxx.''. One must understand that make tries for every prerequisite to either find a file or to match a rule that resolves it. Typical sources of reasons for this error are typos in generated filenames or missing rules that resolve the prerequisite. Use the error or info macros to output generated prerequisite and target strings.
 == Working example ==

@@ Line 57: / Line 57: @@
 * Uses dedicated build result directories allowing to build multiple tool chain variants in the same source tree
-To understand all aspects of the make language is not easy. The good news is that one can pick up a generic makefile and use it benefiting from advanced features without the need to ever touch it. A complete overview of available make commands can be found [https://www.gnu.org/software/make/manual/make.html#Quick-Reference here].
+To understand all aspects of the make language is not easy. The good news is that one can pick up a generic makefile and benefit from advanced features without the need to ever touch it. A complete overview of available make commands can be found [https://www.gnu.org/software/make/manual/make.html#Quick-Reference here].
 <syntaxhighlight lang="make">

@@ Line 16: / Line 16: @@
 == Basic usage ==
-A Makefile consists at its core of rules:
+A Makefile consists of rules:
 <syntaxhighlight lang="make">
@@ Line 22: / Line 22: @@
          recipe
 </syntaxhighlight>
-Each rule is made of the target, which is either a real build result as a executable or library or just a label without a build result. After colon is a list of prerequisites, make will search either for a file for every prerequisite or tries to match a rule to build it. Finally the recipe is a command or list of commands to generate the target. A recipe consists of any shell command but may also contain make variables or macros.
+Each rule is made of the target, which is either a real build result as an executable or library, or just a label without a build result. After the colon there is a list of prerequisites. Make will search for every prerequisite either for a file or tries to match a rule to build it. Finally the recipe is a command or list of commands to generate the target. A recipe consists of any shell command but may also contain make variables or macros.
-A simple Makefile might look like this:
+This is an example for a simple Makefile:
 <syntaxhighlight lang="make">
@@ Line 43: / Line 43: @@
 By calling make without any arguments it will search for any file called makefile or Makefile and pick the first target in the file (indicated in this example by myProg:).
-The default target (the first one in the file) is matched first. Next make searches for the prerequisites, in this example a list of object files to link the executable. Next it either tries to find the object file or execute a rule to build it. In our case there is an explicit rule to build every object file. In case the object file was already build or is a primary source file make will check if the prerequisites are newer than the build result and automatically rebuild this file. This works in a recursive fashion: A target depends on  prerequisites which themselves depend on prerequisites and so on. Make will automatically figure out which parts need to be executed in which order to get it right.
+The default target (the first one in the file) is matched first. Next make searches for the prerequisites, in this example a list of object files to link the executable. Next it either tries to find the object file or execute a rule to build it. In our case there is an explicit rule to build every object file. In case the object file was already build or is a primary source file make will check if the prerequisites are newer than the build result and automatically rebuild this file. This works in a recursive manner: A target depends on  prerequisites which themselves depend on prerequisites and so on. Make will automatically figure out which parts need to be executed in which order to get it right.
 Above example also contains a target which simply triggers a command execution: The clean target does not build anything but automates cleaning up target and intermediate build results.

@@ Line 1: / Line 1: @@
-Make is a build automation tool that automatically builds arbitrary targets (in most cases program executables or libraries) from a list of prerequisites (which can be files or other targets). Make is controlled by reading files called Makefiles which specify how to derive the target. While make is a standard UNIX tool today in most cases people refer to the [https://www.gnu.org/software/make/ GNU make] implementation which provides a lot of extensions.
+Make is a build automation tool, that can build arbitrary targets (in most cases program executables or libraries) from a list of prerequisites (which can be files or other targets). Make is controlled by reading files called Makefiles, which specify how to derive a target. While make is a standard UNIX tool, today in most cases people refer to the [https://www.gnu.org/software/make/ GNU make] implementation, which has a lot of extensions.
@@ Line 7: / Line 7: @@
 The main benefits of using a build automation tool are:
 * Automation :-) of repetitive command execution
-* Consistent build results preventing errors
+* Consistent build results preventing errors even for complex build chains
 * Easier configuration for different tool chains
 * Formulate complex build settings with possibly various targets from the same source tree
 * Automatic matching of prerequisites
-* Speed up compilation by rebuilding only changed source files targets and parallel build support
+* Speed up compilation by rebuilding only changed source file targets and parallel build support
-Any serious software development effort sooner or later has to use a automated build tool. While make is the standard build tool on Linux systems there are various alternatives available, sometimes standalone and sometimes as a frontend to make.
+Any serious software development effort sooner or later has to use an automated build tool. While make is the standard build tool on Linux systems there are various alternatives available, sometimes standalone and sometimes as a frontend to make.
 == Basic usage ==

@@ Line 148: / Line 148: @@
 Parallel build can be enabled using the <code>-j</code> command line switch. Be aware that only source files in the same directory can be processed in parallel. Therefore it is favorable to place all source files in  one directory.
-Debugging makefile errors appears difficult to beginners. It is important to understand that a makefile is not evaluated like a standard programming questions. Instead all instructions are read in and evaluated creating a state machine which is then executed. To track down errors the following make output functions are useful: <code>error</code>, <code>warning</code> and <code>info</code>. The error function will exit the makefile while warning will continue.  You can use those functions to output the expanded value of make variables  or recipes.
+Debugging makefile errors appears difficult to beginners. It is important to understand that a makefile is not evaluated like a standard programming language code. Instead all instructions are read in and evaluated creating a state machine which is then executed. To track down errors the following make output functions are useful: <code>error</code>, <code>warning</code> and <code>info</code>. The error function will exit the makefile while warning will continue.  You can use those functions to output the expanded value of make variables  or recipes.
 == Common Pitfalls ==