OpenMP in Small Bites/False Sharing - Revision history

Simon-schwitanski-3f90@rwth-aachen.de at 10:14, 18 January 2021

2021-01-18T10:14:31Z

2020-12-04T15:28:29Z

Tweak page sorting and title

2020-12-04T14:49:43Z

Remove linebreak

2020-12-04T14:47:14Z

Add DISPLAYTITLE

2020-12-01T08:29:30Z

2020-11-30T18:53:11Z

2020-11-30T18:52:49Z

2020-11-30T18:50:34Z

2020-11-30T15:14:40Z

2020-11-30T15:09:05Z

@@ Line 50: / Line 50: @@
+{
 |type="()"}
-+ Two different memory adresses on the some cache line are accessed by different threads.
++ Two different memory adresses on the same cache line are accessed by different threads.
 || Correct.
 - Two different memory adresses on different cache lines are accessed by the same thread.

@@ Line 1: / Line 1: @@
-[[Category:Tutorials]]<nowiki />
+[[Category:Tutorials|False Sharing (OpenMP)]]<nowiki />
-{{DISPLAYTITLE:False Sharing}}<nowiki />
+{{DISPLAYTITLE:False Sharing (OpenMP)}}<nowiki />
 {{Syllabus OpenMP in Small Bites}}<nowiki />
 __TOC__

@@ Line 1: / Line 1: @@
 [[Category:Tutorials]]<nowiki />
-{{DISPLAYTITLE:False Sharing}}
+{{DISPLAYTITLE:False Sharing}}<nowiki />
 {{Syllabus OpenMP in Small Bites}}<nowiki />
 __TOC__

@@ Line 1: / Line 1: @@
 [[Category:Tutorials]]<nowiki />
 {{Syllabus OpenMP in Small Bites}}<nowiki />
 __TOC__

← Older revision		Revision as of 08:29, 1 December 2020
Line 9:		Line 9:
	<youtube width="600" height="340" right>CMJXvTF-gJk</youtube>		<youtube width="600" height="340" right>CMJXvTF-gJk</youtube>

		+	([[Media:hpc.nrw_04_Introduction-FalseSharing.pdf \| Slides as pdf]])

	== Quiz ==		== Quiz ==

@@ Line 3: / Line 3: @@
 __TOC__
-This video explains the concept of caches in parallel computer architectures, discusses the problem of false sharing, shows how it influences the performance of OpenMP programs and how to avoid it. Further hardware-specific topics which influence the way to develop OpenMP programs is discussed in the part about [[OpenMP_in_Small_Bites/NUMA|Non-Uniform Memory Access]].
+This video explains the concept of caches in parallel computer architectures, discusses the problem of false sharing, shows how it influences the performance of OpenMP programs and how to avoid it. Further hardware-specific topics which influence the way to develop scalable OpenMP programs is discussed in the part about [[OpenMP_in_Small_Bites/NUMA|Non-Uniform Memory Access]].
 == Video ==

@@ Line 15: / Line 15: @@
+{
 |type="()"}
-+ Caches can decrease the performance gap between the cors and the memory.
++ Caches can decrease the performance gap between the cores and the memory.
 || Correct
 - Caches can be used to accelerate the computation in the cores for parallel programs
@@ Line 21: / Line 21: @@
 - Since higher clock frequencies would cause to much heat on the chip, caches are the only way to accelerate the core.
 || Wrong
 </quiz>
 {{hidden end}}

← Older revision		Revision as of 15:09, 30 November 2020
Line 9:		Line 9:

	== Quiz ==		== Quiz ==
		+	{{hidden begin
		+	\|title = 1. What causes the introduction of caches in parallel architectures?
		+	}}
		+	<quiz display=simple>
		+	{
		+	\|type="()"}
		+	+ Caches can decrease the performance gap between the cors and the memory.
		+	\|\| Correct
		+	- Caches can be used to accelerate the computation in the cores for parallel programs
		+	\|\| Wrong
		+	- Since higher clock frequencies would cause to much heat on the chip, caches are the only way to accelerate the core.
		+	\|\| Wrong
		+	</quiz>
		+	{{hidden end}}