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[[Category:Tutorials|Intel VTune Tutorials: CPU Architectures]]<nowiki /> {{DISPLAYTITLE:Intel VTune Tutorial: CPU Architectures}}<nowiki /> {{Syllabus Intel VTune Tutorial}} __TOC__ The second tutorial of the Intel VTune seriers serves as a small interlude, providing some context about CPU architecture concepts. It covers a brief description of the front-end and back-end of a CPU core. These concepts are a necessary basis to understand the language of VTune profiles. === Video === <!--T:5--> <youtube width="600" height="340" right>IlAOa5iUcUU</youtube> ([[Media:VTune_CPUArchitecture.pdf |Slides as pdf]]) === Quiz === <!--T:5--> {{hidden begin |title = 1. How does knowing CPU architecture concepts help with using VTune?}} <quiz display=simple> { |type="()"} + VTunes analysis results are often expressed in these terms. || Correct. It is good to know what "Front End", "Back End", "Bad Speculation" or "Retired Instructions" refer to! - VTune measurements are always presented in a CPU diagram. || Not correct. The data is presented in different ways. This might be a useful gimmick though! - It is impossible to use VTune without a thorough understanding of CPUs! || Not correct. The results can highlight problems on different levels of difficulty. Understanding CPU architecture concepts is a useful basis to discuss results in greater detail. </quiz> {{hidden end}} {{hidden begin |title = 2. What part of the CPU is executing instructions?}} <quiz display=simple> { |type="()"} - The Front-end || Not correct. The front-end is decoding instructions in preparation for the execution. + The Back-end || Correct, the back-end contains the execution engine. - The Cache || Not correct. Caches are used to store frequently used data/instructions close to the execution engine. </quiz> {{hidden end}} {{hidden begin |title = 3. What part of the CPU is preparing instructions for the execution?}} <quiz display=simple> { |type="()"} - The Back-end || Not correct. The back-end is receiving decoded instructions from the front-end and is responsible for their execution. - The Cache || Not correct. Caches are used to store frequently used data/instructions close to the execution engine. + The Front-end || Correct. </quiz> {{hidden end}} {{hidden begin |title = 4. How are profile metrics related to the CPU architecture?}} <quiz display=simple> { |type="()"} - All metrics describe how efficiently data is moved from memory to the CPU. || Not correct. This would not be very useful for programs performing complex computations on few data. - Bad results always highlight inefficiencies in computation. || Not correct. This would not cover performance in moving data, or instruction decoding and speculation in the front-end. + Each metric focusses on a different aspect of the architecture. || Correct. Each metric is affected by its own class of problems. The interpretation and approaches to improvement can be very different between each metric. </quiz> {{hidden end}} {{hidden begin |title = 5. What is a "port" in CPU architectures?}} <quiz display=simple> { |type="()"} - A source of data from network connections. || Not correct. A Network connection is a concept that mostly lives outside of the CPU architecture. + A channel to read/write data from memory or use co-processors. || Correct. The exectution engine moving data from the L1 cache through ports, for example. - CPUs have only a single port, connecting the front-end to the back-end. || Not correct. There are multiple ports. </quiz> {{hidden end}}

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