OpenMP in Small Bites/False Sharing

This video explains the concept of caches in parallel computer architectures, discusses the problem of false sharing, shows how it influences the performance of OpenMP programs and how to avoid it. Further hardware-specific topics which influence the way to develop scalable OpenMP programs is discussed in the part about Non-Uniform Memory Access.

Video

( Slides as pdf)

Quiz

1. What causes the introduction of caches in parallel architectures?

	Caches can decrease the performance gap between the cores and the memory.
	Caches can be used to accelerate the computation in the cores for parallel programs
	Since higher clock frequencies would cause to much heat on the chip, caches are the only way to accelerate the core.

2. Why is false sharing a problem in OpenMP programs?

	Correctness: The parallel program will deliver non-deterministic results.
	Performance: The scalabilty of a parallel program might suffer significantly.
	Compiler: The compiler cannot generate optimal code.

3. What might cause a false sharing effect?

	Two different memory adresses on the same cache line are accessed by different threads.
	Two different memory adresses on different cache lines are accessed by the same thread.
	One memory address is accessed by different threads.