Difference between revisions of "OpenMP in Small Bites/False Sharing"

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OpenMP in Small Bites/False Sharing
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This video explains the concept of caches in parallel computer architectures, discusses the problem of false sharing, shows how it influences the performance of OpenMP programs and how to avoid it. Further hardware-specific topics which influence the way to develop scalable OpenMP programs is discussed in the part about [[OpenMP_in_Small_Bites/NUMA|Non-Uniform Memory Access]].
  
 
== Video ==
 
== Video ==
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<youtube width="600" height="340" right>CMJXvTF-gJk</youtube>
 
<youtube width="600" height="340" right>CMJXvTF-gJk</youtube>
  
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([[Media:hpc.nrw_04_Introduction-FalseSharing.pdf | Slides as pdf]])
  
 
== Quiz ==
 
== Quiz ==
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{{hidden begin
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|title = 1. What causes the introduction of caches in parallel architectures?
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}}
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<quiz display=simple>
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{
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|type="()"}
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+ Caches can decrease the performance gap between the cores and the memory.
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|| Correct
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- Caches can be used to accelerate the computation in the cores for parallel programs
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|| Wrong
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- Since higher clock frequencies would cause to much heat on the chip, caches are the only way to accelerate the core.
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|| Wrong
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</quiz>
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{{hidden end}}
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{{hidden begin
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|title = 2. Why is false sharing a problem in OpenMP programs?
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}}
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<quiz display=simple>
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{
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|type="()"}
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- Correctness: The parallel program will deliver non-deterministic results.
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|| Wrong. False sharing is pure performance problem. Even with false-sharing the results will be determinstic in cache coherent systems.
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+ Performance: The scalabilty of a parallel program might suffer significantly.
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|| Correct.
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- Compiler: The compiler cannot generate optimal code.
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|| Wrong. False sharing is caused by the used hardware, not the compiler.
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</quiz>
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{{hidden end}}
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{{hidden begin
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|title = 3. What might cause a false sharing effect?
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}}
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<quiz display=simple>
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{
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|type="()"}
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+ Two different memory adresses on the same cache line are accessed by different threads.
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|| Correct.
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- Two different memory adresses on different cache lines are accessed by the same thread.
 +
|| Wrong.
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- One memory address is accessed by different threads.
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|| Wrong.
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</quiz>
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{{hidden end}}

Latest revision as of 11:14, 18 January 2021

Tutorial
Title: OpenMP in Small Bites
Provider: HPC.NRW

Contact: tutorials@hpc.nrw
Type: Multi-part video
Topic Area: Programming Paradigms
License: CC-BY-SA
Syllabus

1. Overview
2. Worksharing
3. Data Scoping
4. False Sharing
5. Tasking
6. Tasking and Data Scoping
7. Tasking and Synchronization
8. Loops and Tasks
9. Tasking Example: Sudoku Solver
10. Task Scheduling
11. Non-Uniform Memory Access

This video explains the concept of caches in parallel computer architectures, discusses the problem of false sharing, shows how it influences the performance of OpenMP programs and how to avoid it. Further hardware-specific topics which influence the way to develop scalable OpenMP programs is discussed in the part about Non-Uniform Memory Access.

Video

( Slides as pdf)

Quiz

1. What causes the introduction of caches in parallel architectures?

Caches can decrease the performance gap between the cores and the memory.
Caches can be used to accelerate the computation in the cores for parallel programs
Since higher clock frequencies would cause to much heat on the chip, caches are the only way to accelerate the core.

2. Why is false sharing a problem in OpenMP programs?

Correctness: The parallel program will deliver non-deterministic results.
Performance: The scalabilty of a parallel program might suffer significantly.
Compiler: The compiler cannot generate optimal code.


3. What might cause a false sharing effect?

Two different memory adresses on the same cache line are accessed by different threads.
Two different memory adresses on different cache lines are accessed by the same thread.
One memory address is accessed by different threads.

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